A virtual analog modeling synthesizer in VHDL

(c) 2004 Jürgen Schuhmacher

Unlike with the PLD design, VHDL-Language and high level synthesis in Xilinx ISE are used to generate the VA Synthesis Engine. Here a test design is shown being capable to take an analog voltage from a keyboard (performed by ADC emulation) and produce an analog virtual sound from it. Unlike the known concepts with DDS, a real oscillator is modeled responding with both amplitude and frequency change when energy is applied to the circuit.

Validation-Simulation Key Pressing -> VCO Response

Response of the VCO in case a key is pressed without ADSR curve. Transient, Steady and Roll off are shown. The oscillator thus can be configured as the initial circuit for sound generation as well as a resonance element. Please note the frequency is not stable during acceleration and damping phases.

Front End for Keyboard Input

The functional design of the keyboard input with the virtual voltage derived from pressed keys and the following signal analysis to provide all the signals to control the VCO unit(s). 4 units with individual responses can be attached in this version.

VCO - Synthesis Unit

Logical representation of the FPGA Design. The Virtual Synthesizer controlled by the voltage only. The ideal oscillator from the theory does not work! Only the loss effect based oscillator will reach a stable state, as far as static (= position related) and dynamic (= velocity related) losses are applied the correct and natural way. Non linear losses will make the oscillator respond with non sinus wave which is essential for some instruments. Energy has to be introduced into the circuit to accelerate it and continuously increase the amplitude the natural way. Furthermore white noise will make it oscillate itself by providing enough starting energy. A fine trimming of all the parameters makes sure that the oscillator runs into a stable state during acceleration while also damping is applied. Both damping and acceleration will cause natural behavior of the oscillator in terms of frequency response during acceleration and rollout phase when the note starts and stops. Only during the phase the stable state, the oscillator runs with a static frequency which is the pre calculated resonance frequency from the theory.
 

FPGA - Design Spartan 2 / 3

Physical FPGA Design of the VCO wrapper for one VCO in one FPGA with smoothed asynchronous DAC input of the real analog voltage. Reset Logic is added to control the DCM-PLLs.

Verification - Simulation Frequency Change -> Continuous VCO output

Even if the frequency is changed rapidly without smoothing, the velocity reacts in a continuous (organic) way and oscillator output is smooth and stable with a static amplitude level. No glitches or any other issues do occur.