For music applications it is often necessary to slightly change a given frequency for some percentages. A typical case was the change from consumer audio frequencies of 44,1kHz to 48 kHz used in correct digital audio systems. In digital domains it is not easily possible to resample the clock signal, because the period steps were too coarse. The page Smoothed Frequency Shifting shows a method of direct frequency tuning by adding short delays to the output signal. Performing this dynamically it is possible to change a given clock frequency by only a small percentages.

With this technique is possible to treat any output signal that way to obtain a desired frequency from a given PLL in a modern PLDs or FPGAs. In the image below, a simple block diagram is presented where any of the incoming synch frequencies of a) 44100Hz,  b) 48000Hz and also the new 96000Hz used in modern audio platforms can be changed to any of the other frequencies needed.

In the example the frequency controller is permanently adjusted that way to add enough delays to lower the frequency down to 104,4x MHz which is a multiple of 44,1kHz x 64 - the required S/PDIF frequency for such a digital system. In the same way one can easily create an appropriate multiple of 96kHz. The frequency can be filtered the analog way if necessary to remove jitter and the fed back into the FPGA in order to drive the resampling filter for the data.

The resampler is built with an input synchronizer (asynchronous FIFO) a clock domain cross circuit with eventual interpolation and both a cascaded integrated comb filter known as Hogenauer's filter and an attached steep low cut at 22500 Hz, 24000 Hz to perform anti aliasing filtering.

Conclusion

Modern PLDs and FPGAs can be used to easily interchange data in between all given sample rates used in existent audio systems these days without making use of external chips or resamplers.