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PLD SYNTH Module
48kHz x 16 Bit
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FPGA-Platform
Xilnx
Spartan 3E
An Spartan
3E platform is used to implement a design for my
PLD-Synthesiser.

The circuit is a complete VHDL-implementation of my music
synthesizer formerly built for Xilinx XC4000 PLDs and following.
Because of the greater resources, some additional function could
be integrated, already tested in the C-Version on my chameleon synthesiser.
Circuit Function
The design uses
the DDS method with a given tuning word. This is derived from a
frequency information of the MIDI word and progresses a phase counter.
Together with the vibrato information, this generates a phase value
for to the waveform generators.

The phase counter is directly used as a sawtooth. The
triangle is generated by flipping the bits partially when the
phase counter is greater than 50%. The sine wave is used by
super imposing waves: The third harmonic is subtracted from the
actual triangle. The phase of that harmonic is generated by
shift-and-add processing like f-sine = tria(f) * 3 + tria (3f).
This produces almoset a good sine-like tone.

The quality
could be furtherly increased if the chip had more resources to
implement more waves. With forthcoming FPGAs
more waves shall be possible. Due to limited space, modulation
via the parameters and the ADSR is also still coarse in
comparison to analoge synthesisers.
Read about the former
circuit PLD-Synthesiser
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